Illumina HiSeq BclConverter

[wdt]

Is it possible to do one lane at a time Bcl -> QSEQ.txt conversion using BclConveter? Can someone show the exact command ?

Here is what I have been using

~bin/setupBclToQseq.py -i FOLDER_CONTAINING_LANE_DIRS -p POSITION_DIR -o OUT_DIR --overwrite

followed by make in OUT_DIR

My command stopped at lane 6 because some file was missing , but I'd like to continue with lanes 7 and 8.
Should I be using make -j 8 so all lanes are processed simultaneously?

Is there a '--lane=N" option for one lane at a time conversion?

[mgogol]

These are the commands I usually use:

~/BclConverter-1.7.1/bin/setupBclToQseq.py -i /solexa/*62P5DAAXX/Data/Intensities/BaseCalls -p /solexa/*62P5DAAXX/Data/Intensities -o /solexa/*62P5DAAXX/Data/Intensities/BaseCalls --in-place --overwrite
nohup make -j 8 > ./make.out 2> make.err

If I got an error like that, I think I'd follow up with techsupport@illumina.com. I've had quite good experiences with them.

[jeny]

Hi,

I asked this to illumina techsupport a while ago, and their answer was :
The BCL converter doesn't allow you to specify lanes. I would strongly recommend not to split a RunFolder apart until after you have the qseq files. You could then run a couple of different GERALD jobs to split lanes apart. I wouldn't do it before that stage.
So, there is not "--lane" option as you would like.

[wdt]

Digging a little deeper, I found that "stats" file is missing for "28" and "43", which might have led to unsuccessful conversion. (See below)

Any ideas?

Thanks,


Data/Intensities/BaseCalls/L006/C9.1 $ ls -1

s_6_1.bcl
s_6_1.stats
s_6_21.bcl
s_6_21.stats
s_6_22.bcl
s_6_22.stats
s_6_23.bcl
s_6_23.stats
s_6_24.bcl
s_6_24.stats
s_6_25.bcl
s_6_25.stats
s_6_26.bcl
s_6_26.stats
s_6_27.bcl
s_6_27.stats
s_6_28.bcl
s_6_2.bcl
s_6_2.stats
s_6_3.bcl
s_6_3.stats
s_6_41.bcl
s_6_41.stats
s_6_42.bcl
s_6_42.stats
s_6_43.bcl
s_6_44.bcl
s_6_44.stats
s_6_45.bcl
s_6_45.stats
s_6_46.bcl
s_6_46.stats
s_6_47.bcl
s_6_47.stats
s_6_48.bcl
s_6_48.stats
s_6_4.bcl
s_6_4.stats
s_6_5.bcl
s_6_5.stats
s_6_61.bcl
s_6_61.stats
s_6_62.bcl
s_6_62.stats
s_6_63.bcl
s_6_63.stats
s_6_64.bcl
s_6_64.stats
s_6_65.bcl
s_6_65.stats
s_6_66.bcl
s_6_66.stats
s_6_67.bcl
s_6_67.stats
s_6_68.bcl
s_6_68.stats
s_6_6.bcl
s_6_6.stats
s_6_7.bcl
s_6_7.stats
s_6_8.bcl
s_6_8.stats

[gerald2545]

rerun setupBclToQseq.py
go into your output directory
edit Makefile.config file
from the line : lanes := s_1 s_2 s_3 s_4 s_5 s_6 s_7 s_8, delete the lanes for which you don't want the qseq and delete the corresponding s_?_tiles lines

In the s_?_tiles you are interested in, delete the tiles for which you have your problem.

for your case, you would have :

lanes :=  s_6 s_7 s_8
s_6_tiles := 0001 0002 0003 0004 0005 0006 0007 0008 0021 0022 0023 0024 0025 0026 0027 0041 0042 0044 0045 0046 0047 0048 0061 0062 0063 0064 0065 0066 0067 0068
s_7_tiles := 0001 0002 0003 0004 0005 0006 0007 0008 0021 0022 0023 0024 0025 0026 0027 0028 0041 0042 0043 0044 0045 0046 0047 0048 0061 0062 0063 0064 0065 0066 0067 0068
s_8_tiles := 0001 0002 0003 0004 0005 0006 0007 0008 0021 0022 0023 0024 0025 0026 0027 0028 0041 0042 0043 0044 0045 0046 0047 0048 0061 0062 0063 0064 0065 0066 0067 0068

then run the make or qmake command to generate the wanted qseq files.

You can then get the missing qseq files for tiles s_6_28 and s_6_43 using Bustard. Please have a look à the manual as you can specify only the tiles you are interested in.

Regards

Gérald

[wdt]

Thanks, Gerald. This is very helpful.

[wanfahmi]

BCL Conversion for this run stopped at lane 4 with the following error:

Error: /storage/BclConverter-1.7.1/c++/basecalling/BclToQseqConverter.cpp: unsigned int ga::basecalling::BclReader::readNumberOfClusters(): line 122: 2010-Nov-30 13:39:36: Invalid argument: Incorrect number of clusters in /storage/101116_ILLUMINA-E84855_00027_FC_BLACKH348pM/Data/Intensities/BaseCalls/L004/C99.1/s_4_39.bcl: expected 478507: got 0

# Why there is no cluster or incorrect cluster?
# How would I solve this problem

Thank you!

[wdt]

As per a suggestion on this forum, I contacted the Illumina tech-support at techsupport@illumina.com and they got back with me very quickly.

It is worth trying for BclConversion issues.

good luck.

[AndrewWhite]

To skip a lane, just create in the make directory an empty file s_N_finished.txt
where N stands for the lane number. In order to redo some lane, delete the corresponding "finished.txt" file and run make again.

[jjw]

Hi wanfahmi,

I got the same problem as you. Did you manage to solve it in the end?
Thanks very much!
JJ

[HMorrison]

We have a new HiSeq1000 and cannot get .bcl converted to fastq or qseq. Were told (by someone from illumina) that BCL converter standalone package won't work with HiSeq; OLB won't install readily (fftw issues), CASAVA 1.7 doesn't include converter and CASAVA 1.8 isn't available yet. Why is there such a disconnect between the RTA and alignment/assembly steps?